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ds07-12531-2e fujitsu semiconductor data sheet 8-bit proprietary microcontroller cmos f 2 mc-8l mb89630r series mb89635r/t635r/636r/637r/t637r mb89p637/w637/pv630 n outline the mb89630r series has been developed as a general-purpose version of the f 2 mc*-8l family consisting of proprietary 8-bit, single-chip microcontrollers. in addition to a compact instruction set, the microcontrollers contain a variety of peripheral functions such as dual-clock control system, five operating speed control stages, a uart, timers, a pwm timer, a serial interface, an a/d converter, an external interrupt, and a watch prescaler. *: f 2 mc stands for fujitsu flexible microcontroller. n features ? high-speed operating capability at low voltage ? minimum execution time: 0.4 m s@3.5 v, 0.8 m s@2.7 v ?f 2 mc-8l family cpu core ? five types of timers 8-bit pwm timer: 2 channels (also usable as a reload timer) 8-bit pulse-width count timer (continuous measurement capable, applicable to remote control, etc.) 16-bit timer/counter 21-bit timebase timer ?uart clk-synchronous/clk-asynchronous data transfer capable (6, 7, and 8 bits) ? serial interface switchable transfer direction to allows communication with various equipment. ? 10-bit a/d converter start by an external input capable (continued) multiplication and division instructions 16-bit arithmetic operations test and branch instructions bit manipulation instructions, etc. instruction set optimized for controllers
mb89630r series 2 (continued) ? external interrupt: 4 channels four channels are independent and capable of wake-up from low-power consumption modes (with an edge detection function). ? low-power consumption modes stop mode (oscillation stops to minimize the current consumption.) sleep mode (the cpu stops to reduce the current consumption to approx. 1/3 of normal.) subclock mode watch mode ? bus interface function with hold and ready function n pac k ag e 64-pin plastic sh-dip (dip-64p-m01) 64-pin ceramic sh-dip (dip-64c-a06) 64-pin plastic qfp (fpt-64p-m06) 64-pin ceramic mqfp (mqp-64c-p01) 64-pin plastic qfp (fpt-64p-m09) 64-pin ceramic mdip (mdp-64c-p02)
mb89630r series 3 n product lineup (continued) mb89636r mb89637r mb89t635r mb89t637r mb89p637 mb89w637 mb89pv630 classification mass-produced products (mask rom products) external rom products one-time prom product eprom product piggyback/ evaluation product (for evaluation and development) rom size 16 k 8 bits (internal mask rom) 24 k 8 bits (internal mask rom) 32 k 8 bits (internal mask rom) fixed to external rom 32 k 8 bits (internal prom, to be programmed with general-purpose eprom programmer) 32 k 8 bits (external rom) ram size 512 8 bits 768 8 bits 1024 8 bits 512 8 bits 1024 8 bits 1 k 8 bits cpu functions the number of instructionns: 136 instruction bit length: 8 bits instruction length: 1 to 3 bytes data bit length: 1, 8, 16 bits minimum execution time: 0.4 to 6.4 m s/10 mhz, 61 m s@32.768 khz interrupt processing time: 3.6 to 57.6 m s/10 mhz, 562.5 m s@32.768 khz ports input ports: 5 (all also serve as peripherals.) output ports (n-ch open-drain): 8 (all also serve as peripherals.) i/o ports (n-ch open-drain): 4 (all also serve as peripherals.) output ports (cmos): 8 (all also serve as bus control.) i/o ports (cmos): 28 (27 ports also serve as bus pins and peripherals.) total: 53 clock timer 21 bits 1 (in main clock)/15 bits 1 (at 32.768 khz) 8-bit pwm timer 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 m s to 3.3 ms) 2 channels 7/8-bit resolution pwm operation (conversion cycle: 51.2 m s to 839 ms) 2 channels 8-bit pulse width count timer 8-bit timer operation (overflow output capable, operating clock cycle: 0.4 to 12.8 m s) 8-bit reload timer operation (toggled output capable, operating clock cycle: 0.4 to 12.8 m s) 8-bit pulse width measurement operation (capable of continuous measurement, and measurement of h pulse width/ l pulse width/ from - to - /from to ) 16-bit timer/ counter 16-bit timer operation (operating clock cycle: 0.4 m s) 16-bit event counter operation (rising edge/falling edge/both edge selectable) 8-bit serial i/o 8 bits lsb first/msb first selectable one clock selectable from four transfer clocks (one external shift clock, three internal shift clocks: 0.8 m s, 3.2 m s, 12.8 m s) uart capable of switching two i/o systems by software transfer data length (6, 7, and 8 bits) transfer rate (300 to 62500 bps. at 10 mhz osciliation) 10-bit a/d converter 10-bit resolution 8 channels a/d conversion mode (conversion time: 13.2 m s) sense mode (conversion time: 7.2 m s) capable of continuous activation by an external activation or an internal timer mb89635r part number item
mb89630r series 4 (continued) * : varies with conditions such as the operating frequency. (see section n electrical characteristics.) in the case of the mb89pv630, the voltage varies with the restrictions of the eprom for use. n package and corresponding products : available : not available * : to convert pin pitches, an adapter socket (manufacturer: sun hayato co., ltd.) is available. 64sd-64qf2-8l: for conversion from (dip-64p-m01, dip-64c-a06, or mdp-64c-p02) to fpt-64p-m09 inquiry: sun hayato co., ltd.: tel (81)-3-3986-0403 fax (81)-3-5396-9106 note: for more information about each package, see section n package dimensions. mb89636r mb89637r mb89t635r mb89t637r mb89p637 mb89w637 mb89pv630 external interrupt input 4 independent channels (edge selection, interrupt vector, source flag). rising edge/falling edge selectable used also for wake-up from stop/sleep mode. (edge detection is also permitted in stop mode.) standby mode sleep mode, stop mode, watch mode, and subclock mode process cmos operating voltage* 2.2 v to 6.0 v 2.7 v to 6.0 v eprom for use mbm27c256a-20cz mbm27c256a-20tv package mb89635r mb89t635r mb89636r mb89637r mb89t637r mb89p637 mb89w637 mb89pv630 dip-64p-m01 fpt-64p-m06 fpt-64p-m09 * * * dip-64c-a06 mqp-64c-p01 mdp-64c-p02 mb89635r part number item
mb89630r series 5 n differences among products 1. memory size before evaluating using the piggyback product, verify its differences from the product that will actually be used. take particular care on the following points: on the mb89p637/w637, the program area starts from address 8007 h but on the mb89pv630 and mb89637r starts from 8000 h . ? on the mb89p637/w637, addresses 8000 h to 8006 h comprise the option setting area, option settings can be read by reading these addresses. on the mb89pv630/mb89637r, addresses 8000 h to 8006 h could also be used as a program rom. however, do not use these addresses in order to maintain compatibility of the mb89p637/w637. ? the stack area, etc., is set at the upper limit of the ram. ? the external area is used. 2. current consumption ? in the case of the mb89pv630, add the current consumed by the eprom which connected to the top socket. ? when operated at low speed, the product with an otprom (one-time prom) or an eprom will consume more current than the product with a mask rom. however, the current consumption in sleep/stop modes is the same. (for more information, see sections n electrical characteristics and n example characteristics.) 3. mask options functions that can be selected as options and how to designate these options vary by the product. before using options check section n mask options. take particular care on the following points: ? a pull-up resistor cannot be set for p50 to p53 on the mb89p637 and mb89w637. ? options are fixed on the mb89pv630, mb89t635r, and mb89t637r. 4. differences between the mb89630 and mb89630r series ? memory access area there are no difference between the access area of mb89635/mb89635r, and that of mb89637/mb89637r. the access area of mb89636 is different from that of the mb89636r when using in external bus mode. address memory area mb89636 mb89636r 0000 h to 007f h i/o area i/o area 0080 h to 037f h ram area ram area 0380 h to 047f h external area access prohibited 0480 h to 7fff h external area 8000 h to 9fff h access prohibited a000 h to ffff h rom area rom area
mb89630r series 6 ? other specifications both mb89630 series and mb89630r is the same. ? electrical specifications/electrical characteristics electrical specifications of the mb89630r series are the same as that of the mb89630 series. electrical characteristics of both the series are much the same. n correspondence between the mb89630 and mb89630r series ? the mb89630r series is the reduction version of the mb89630 series. ? the the mb89630 and mb89630r series consist of the following products: mb89630 series mb89635 mb89t635 mb89636 mb89637 mb89t637 mb89p637 mb89w637 mb89pv630 mb89630r series mb89635r mb89t635r mb89636r mb89637r mb89t637r
mb89630r series 7 n pin assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 p51/bz p50/adst p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 av cc avr av ss p74/ec p73/int3 p72/int2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p00/ad0 p01/ad1 p02/ad2 p03/ad3 p04/ad4 p05/ad5 p06/ad6 p07/ad7 p10/a08 p11/a09 p12/a10 p13/a11 p14/a12 p15/a13 p16/a14 p17/a15 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 p52 p53/pto2 p40/uck2 p41/uo2 p42/ui2 p43/pto1 p30/uck1 p31/uo1 v cc p32/ui1 p33/sck1 p34/so1 p35/si1 p36/pwc p37/wto v ss 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 p71/int1/x0a* p70/int0/x1a* rst mod0 mod1 x0 x1 v ss p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc (top view) (fpt-64p-m09) *: when the dual-clock system is selected. (dip-64p-m01) (dip-64c-a06) (mdp-64c-p02) (top view) 65 v pp 66 a12 67 a7 68 a6 69 a5 70 a4 71 a3 72 a2 73 a1 74 a0 75 o1 76 o2 77 o3 78 v ss v cc 92 a14 91 a13 90 a8 89 a9 88 a11 87 oe 86 a10 85 ce 84 o8 83 o7 82 o6 81 o5 80 o4 79 1 p31/uo1 2 p30/uck1 3 p43/pto1 4 p42/ui2 5 p41/uo2 6 p40/uck2 7 p53/pto2 8 p52 9 p51/bz 10 p50/adst 11 p60/an0 12 p61/an1 13 p62/an2 14 p63/an3 15 p64/an4 16 p65/an5 17 p66/an6 18 p67/an7 19 av cc 20 avr 21 av ss 22 p74/ec 23 p73/int3 24 p72/int2 25 p71/int1/x0a* 26 p70/int0/x1a* 27 rst 28 mod0 29 mod1 30 x0 31 x1 32 v ss v cc 64 p32/ui1 63 p33/sck1 62 p34/so1 61 p35/si1 60 p36/pwc 59 p37/wto 58 v ss 57 p00/ad0 56 p01/ad1 55 p02/ad2 54 p03/ad3 53 p04/ad4 52 p05/ad5 51 p06/ad6 50 p07/ad7 49 p10/a08 48 p11/a09 47 p12/a10 46 p13/a11 45 p14/a12 44 p15/a13 43 p16/a14 42 p17/a15 41 p20/bufc 40 p21/hak 39 p22/hrq 38 p23/rdy 37 p24/clk 36 p25/wr 35 p26/rd 34 p27/ale 33 each pin inside the dashed line is for mb89pv630 only. *: when the dual-clock system is selected.
mb89630r series 8 ? pin assignment on package top (mb89pv630 only) n.c.: internally connected. do not use. pin no. pin name pin no. pin name pin no. pin name pin no. pin name 65 n.c. 73 a2 81 n.c. 89 oe 66 v pp 74 a1 82 o4 90 n.c. 67a1275a083o591a11 68 a7 76 n.c. 84 o6 92 a9 69 a6 77 o1 85 o7 93 a8 70 a5 78 o2 86 o8 94 a13 71 a4 79 o3 87 ce 95 a14 72 a3 80 v ss 88 a10 96 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 p52 p51/bz p50/adst p60/an0 p61/an1 p62/an2 p63/an3 p64/an4 p65/an5 p66/an6 p67/an7 av cc avr av ss p74/ec p73/int3 p72/int2 p71/int1/x0a* p70/int0/x1a* 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p37/wto v ss p00/ad0 p01/ad1 p02/ad2 p03/ad3 p04/ad4 p05/ad5 p06/ad6 p07/ad7 p10/a08 p11/a09 p12/a10 p13/a11 p14/a12 p15/a13 p16/a14 p17/a15 p20/bufc 64 63 62 61 60 59 58 57 56 55 54 53 52 p53/pto2 p40/uck2 p41/uo2 p42/ui2 p43/pto1 p30/uck1 p31/uo1 v cc p32/ui1 p33/sck1 p34/so1 p35/si1 p36/pwc 20 21 22 23 24 25 26 27 28 29 30 31 32 rst mod0 mod1 x0 x1 v ss p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak 85 86 87 88 89 90 91 92 93 77 76 75 74 73 72 71 70 69 84 83 82 81 80 79 78 94 95 96 65 66 67 68 (top view) (fpt-64p-m06) (mqp-64c-p01) each pin inside the dashed line is for mb89pv630 only. *: when the dual-clock system is selected.
mb89630r series 9 n pin description (continued) *1: dip-64p-m01, dip-64c-a06 *4: fpt-64p-m06 *2: mdp-64c-p02 *5: mqp-m64c-p01 *3: fpt-64p-m09 pin no. pin name circuit type function sh-dip *1 mdip *2 qfp2 *3 qfp1 *4 mqfp *5 30 22 23 x0 a main clock crystal oscillator pins 31 23 24 x1 28 20 21 mod0 d operating mode selection pins connect directly to v cc or v ss . 29 21 22 mod1 27 19 20 rst c reset i/o pin this pin is an n-ch open-drain output type with a pull-up resistor, and a hysteresis input type. l is output from this pin by an internal reset source. the internal circuit is initialized by the input of l. 56 to 49 48 to 41 49 to 42 p00/ad0 to p07/ad7 f general-purpose i/o ports when an external bus is used, these ports function as the multiplex pins of the lower address output and the data i/o. 48 to 41 40 to 33 41 to 34 p10/a08 to p17/a157 f general-purpose i/o ports when an external bus is used, these ports function as an upper address output. 40 32 33 p20/bufc h general-purpose output port when an external bus is used, this port can also be used as a buffer control output by setting the bctr. 39 31 32 p21/hak h general-purpose output port when an external bus is used, this port can also be used as a hold acknowledge by setting the bctr. 38 30 31 p22/hrq f general-purpose output port when an external bus is used, this port can also be used as a hold request input by setting the bctr. 37 29 30 p23/rdy f general-purpose output port when an external bus is used, this port functions as a ready input. 36 28 29 p24/clk h general-purpose output port when an external bus is used, this port functions as a clock output. 35 27 28 p25/wr h general-purpose output port when an external bus is used, this port functions as a write signal output. 34 26 27 p26/rd h general-purpose output port when an external bus is used, this port functions as a read signal output.
mb89630r series 10 (continued) (continued) *1: dip-64p-m01, dip-64c-a06 *4: fpt-64p-m06 *2: mdp-64c-p02 *5: mqp-m64c-p01 *3: fpt-64p-m09 pin no. pin name circuit type function sh-dip *1 mdip *2 qfp2 *3 qfp1 *4 mqfp *5 33 25 26 p27/ale h general-purpose output port when an external bus is used, this port functions as an address latch signal output. 2 58 59 p30/uck1 g general-purpose i/o port also serves as the clock i/o 1 for the uart. this port is a hysteresis input type. 1 57 58 p31/uo1 f general-purpose i/o port also serves as the data output 1 for the uart. 63 55 56 p32/ui1 g general-purpose i/o port also serves as the data input 1 for the uart. this port is a hysteresis input type. 62 54 55 p33/sck1 g general-purpose i/o port also serves as the data input for the 8-bit serial i/o. this port is a hysteresis input type. 61 53 54 p34/so1 f general-purpose i/o port also serves as the data output for the 8-bit serial i/o. 60 52 53 p35/si1 g general-purpose i/o port also serves as the data input for the 8-bit serial i/o. this port is a hysteresis input type. 59 51 52 p36/pwc g general-purpose i/o port also serves as the measured pulse input for the 8-bit pulse width counter. this port is a hysteresis input type. 58 50 51 p37/wto f general-purpose i/o port also serves as the toggle output for the 8-bit pulse width counter. 6 62 63 p40/uck2 g general-purpose i/o port also serves as the clock i/o 2 for the uart. this port is a hysteresis input type. 5 61 62 p41/uo2 f general-purpose i/o port also serves as the data output 2 for the uart. 4 60 61 p42/ui2 g general-purpose i/o port also serves as the data input 2 for the uart. this port is a hysteresis input type. 3 59 60 p43/pto1 f general-purpose i/o port also serves as the toggle output for the 8-bit pwm timer. 10 2 3 p50/adst k general-purpose i/o port also serves as an a/d converter external activation. this port is a hysteresis input type.
mb89630r series 11 (continued) *1: dip-64p-m01, dip-64c-a06 *4: fpt-64p-m06 *2: mdp-64c-p02 *5: mqp-m64c-p01 *3: fpt-64p-m09 pin no. pin name circuit type function sh-dip *1 mdip *2 qfp2 *3 qfp1 *4 mqfp *5 9 1 2 p51/bz j general-purpose i/o port also serves as a buzzer output. 8 64 1 p52 j general-purpose i/o port 7 63 64 p53/pto2 j general-purpose i/o port also serves as the toggle output for the 8-bit pwm timer. 11 to 18 3 to 10 4 to 11 p60/an0 to p67/an7 i n-ch open-drain output ports also serve as an a/d converter analog input. 26, 25 18, 17 19, 18 p70/int0/x1a, p71/int1/x0a b/e input-only ports these ports are a hysteresis input type. also serve as an external interrupt input (at single- clock operation). subclock crystal oscillator pins (at dual-clock operation) 24, 23 16, 15 17, 16 p72/int2, p73/int3 e input-only ports also serve as an external interrupt input. these ports are a hysteresis input type. 22 14 15 p74/ec e general-purpose input port also serves as the external clock input for the 16-bit timer/counter. this port is a hysteresis input type. 64 56 57 v cc power supply pin 32, 57 24,49 25, 50 v ss power supply (gnd) pin 19 11 12 av cc a/d converter power supply pin 20 12 13 avr a/d converter reference voltage input pin 21 13 14 av ss a/d converter power supply pin use this pin at the same voltage as v ss .
mb89630r series 12 external eprom pins (mb89pv630 only) pin no. pin name i/o function mdip mqfp 65 66 v pp o h level output pin 66 67 68 69 70 71 72 73 74 67 68 69 70 71 72 73 74 75 a12 a7 a6 a5 a4 a3 a2 a1 a0 o address output pins 75 76 77 77 78 79 o1 o2 o3 i data input pins 78 80 v ss o power supply (gnd) pin 79 80 81 82 83 82 83 84 85 86 o4 o5 o6 o7 o8 i data input pins 84 87 ce o rom chip enable pin outputs h during standby. 85 88 a10 o address output pin 86 89 oe o rom output enable pin outputs l at all times. 87 88 89 91 92 93 a11 a9 a8 o address output pins 90 94 a13 o 91 95 a14 o 92 96 v cc o eprom power supply pin 65 76 81 90 n.c. internally connected pins be sure to leave them open.
mb89630r series 13 n i/o circuit type (continued) type circuit remarks a ? crystal or ceramic oscillation type (main clock) external clock input selection versions of mb89pv630, mb89p637, mb89w637, mb89635r, mb89t635r, mb89636r, mb89637r, and mb89t637r at an oscillation feedback resistor of approximately 1 m w @5.0 v b ? crystal or ceramic oscillation type (subclock) mb89pv630, mb89p637, mb89w637, mb89635r, mb89636r, and mb89637r with dual-clock system at an oscillation feedback resistor of approximately 4.5 m w @5.0 v c ? at an output pull-up resistor (p-ch) of approximately 50 k w @5.0 v ? hysteresis input d e ? hysteresis input ? pull-up resistor optional (except p70 and p71) f ? cmos output ?cmos input ? pull-up resistor optional (except p22 and p23) x1 x0 standby control signal x1a x0a standby control signal r p-ch n-ch r p-ch n-ch p-ch r
mb89630r series 14 (continued) type circuit remarks g ? cmos output ? hysteresis input ? pull-up resistor optional h ? cmos output i ? analog input j?cmos input ? pull-up resistor optional k ? hysteresis input ? pull-up resistor optional p-ch n-ch p-ch r p-ch n-ch analo g input n-ch n-ch r p-ch n-ch r p-ch
mb89630r series 15 n handling devices 1. preventing latchup latchup may occur on cmos ics if voltage higher than v cc or lower than v ss is applied to input and output pins other than medium- and high-voltage pins or if higher than the voltage which shows on 1. absolute maximum ratings in section n electrical characteristics is applied between v cc and v ss . when latchup occurs, power supply current increases rapidly and might thermally damage elements. when using, take great care not to exceed the absolute maximum ratings. also, take care to prevent the analog power supply (av cc and avr) and analog input from exceeding the digital power supply (v cc ) when the analog system power supply is turned on and off. 2. treatment of unused input pins leaving unused input pins open could cause malfunctions. they should be connected to a pull-up or pull-down resistor. 3. treatment of power supply pins on microcontrollers with a/d and d/a converters connect to be av cc = davc = v cc and av ss = avr = v ss even if the a/d and d/a converters are not in use. 4. treatment of n.c. pins be sure to leave (internally connected) n.c. pins open. 5. power supply voltage fluctuations although v cc power supply voltage is assured to operate within the rated range, a rapid fluctuation of the voltage could cause malfunctions, even if it occurs within the rated range. stabilizing voltage supplied to the ic is therefore important. as stabilization guidelines, it is recommended to control power so that v cc ripple fluctuations (p-p value) will be less than 10% of the standard v cc value at the commercial frequency (50 hz to 60 hz) and the transient fluctuation rate will be less than 0.1 v/ms at the time of a momentary fluctuation such as when power is switched. 6. precautions when using an external clock when an external clock is used, oscillation stabilization time is required even for power-on reset (option selection) and wake-up from stop mode.
mb89630r series 16 n programming to the eprom on the mb89p637 the mb89p637 is an otprom version of the mb89630 series. 1. features ? 32-kbytes prom on chip ? options can be set using the eprom programmer. ? equivalency to the mbm27c256a in eprom mode (when programmed with the eprom programmer) 2. memory space memory space in each mode is illustrated below. 3. programming to the epprom in eprom mode, the mb89p637 functions equivalent to the mbm27c256a. this allows the prom to be programmed with a general-purpose eprom programmer by using the dedicated socket adapter. however, the electronic signature mode cannot be used. when the operating rom area for a single chip is 32 kbytes (8007 h to ffff h ) the eprom can be programmed as follows: program area (eprom) 32 kb 7fff h option setting area 0000 h option setting area 0007 h prom 32 kb external area i/o register ram 0000 h 0080 h 0100 h 0200 h 0480 h 8000 h 8007 h ffff h normal operating mode eprom mode (corresponding addresses on the eprom programmer)
mb89630r series 17 programming procedure (1) set the eprom programmer to the mbm27c256a-20cz and mbm27c256a-20tv. (2) load program data into the eprom programmer at 0007 h to 7fff h . (note that addresses 8000 h to ffff h in the operating mode assign to 0000 h to 7fff h in eprom mode). (3) load option data into addresses 0000 h to 0006 h of the eprom programmer. (for information about each corresponding option, see 8. otprom option bit map.) (4) program with the eprom programmer. 4. recommended screening conditions high-temperature aging is recommended as the pre-assembly screening procedure for a product with a blanked otprom microcomputer program. 5. programming yield all bits cannot be programmed at fujitsu shipping test to a blanked otprom microcomputer, due to its nature. for this reason, a programming yield of 100% cannot be assured at all times. 6. erasure in order to clear all locations of their programmed contents, it is necessary to expose the internal eprom to an ultraviolet light source. a dosage of 10 w-seconds/cm 2 is required to completely erase an internal eprom. this dosage can be obtained by exposure to an ultraviolet lamp (wavelength of 2537 angstroms (?)) with intensity of 12000 m w/cm 2 for 15 to 21 minutes. the internal eprom should be about one inch from the source and all filters should be removed from the uv light source prior to erasure. it is important to note that the internal eprom and similar devices, will erase with light sources having wave- lengths shorter than 4000 ?. although erasure time will be much longer than with uv source at 2537 ?, nevertheless the exposure to fluorescent light and sunlight will eventually erase the internal eprom, and exposure to them should be prevented to realize maximum system reliability. if used in such an environment, the package windows should be covered by an opaque label or substance. program, verify aging +150 c, 48 hrs. data verification assembly
mb89630r series 18 7. eprom programmer socket adapter inquiry: sun hayato co., ltd.: tel : (81)-3-3986-0403 fax : (81)-3-5396-9106 8. otprom option bit map note: each bit is set to 1 as the initialized value. part no. mb89p637-sh mb89p637pf package sh-dip-64 qfp-64 compatible socket adapter sun hayato co., ltd. rom-64sd-28dp-8l rom-64qf-28dp-8l address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0000 h vacancy readable and writable vacancy readable and writable vacancy readable and writable single/dual- clock system 1: dual clock 0: single clock reset pin output 1: yes 0: no power-on reset 1: yes 0: no oscillation stabilization (/f ch ) 11:2 18 /f ch 01:2 17 /f ch 10:2 14 /f ch 00:2 4 /f ch 0001 h p07 pull-up 1: no 0: yes p06 pull-up 1: no 0: yes p05 pull-up 1: no 0: yes p04 pull-up 1: no 0: yes p03 pull-up 1: no 0: yes p02 pull-up 1: no 0: yes p01 pull-up 1: no 0: yes p00 pull-up 1: no 0: yes 0002 h p17 pull-up 1: no 0: yes p16 pull-up 1: no 0: yes p15 pull-up 1: no 0: yes p14 pull-up 1: no 0: yes p13 pull-up 1: no 0: yes p12 pull-up 1: no 0: yes p11 pull-up 1: no 0: yes p10 pull-up 1: no 0: yes 0003 h p37 pull-up 1: no 0: yes p36 pull-up 1: no 0: yes p35 pull-up 1: no 0: yes p34 pull-up 1: no 0: yes p33 pull-up 1: no 0: yes p32 pull-up 1: no 0: yes p31 pull-up 1: no 0: yes p30 pull-up 1: no 0: yes 0004 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable p43 pull-up 1: no 0: yes p42 pull-up 1: no 0: yes p41 pull-up 1: no 0: yes p40 pull-up 1: no 0: yes 0005 h vacancy readable and writable vacancy readable and writable vacancy readable and writable p74 pull-up 1: no 0: yes p73 pull-up 1: no 0: yes p72 pull-up 1: no 0: yes vacancy readable and writable vacancy readable and writable 0006 h vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable vacancy readable and writable reserved bit readable and writable
mb89630r series 19 n programming to the eprom with piggyback/evaluation device 1. eprom for use mbm27c256a-20cz, mbm27c256a-20tv 2. programming socket adapter to program to the prom using an eprom programmer, use the socket adapter (manufacturer: sun hayato co., ltd.) listed below. inquiry: sun hayato co., ltd.: tel: (81)-3-3986-0403 fax : (81)-3-5396-9106 3. memory space memory space in each mode, such as 32-kbyte prom, option area is diagrammed below. 4. programming to the eprom (1) set the eprom programmer to the mbm27c256a. (2) load program data into the eprom programmer at 0007 h to 7fff h . (3) program to 0000 h to 7fff h with the eprom programmer. package adapter socket part number lcc-32 (rectangle) rom-32lc-28dp-yg prom 32 kb ffff h 0000 h 8000 h 0080 h 0480 h not available single chip address i/o corresponding addresses on the eprom programmer ram 8007 h not available 7fff h 0000 h 0007 h eprom 32 kb not available
mb89630r series 20 n block diagram subclock oscillator (32.768 khz) rst clock controller reset circuit (watchdog timer) 8 8 p00/ad0 to p07/ad7 p10/a08 to p17/a15 cmos i/o port external bus interface mod0 mod1 p27/ale p26/rd p25/wr p24/clk p23/rdy p22/hrq p21/hak p20/bufc cmos output port ram f mc-8l cpu rom v cc 2, v ss 2 other pins 21-bit timebase timer 8-bit pwc timer uart cmos i/o port 8-bit pwm timer buzzer output input port 16-bit timer/counter 4 p73/int3 p74/ec p50/adst p51/bz p52 p53/pto2 p43/pto1 p33/sck1 p34/so1 p36/pwc x0a x1a watch prescaler cmos i/o port p37/wto p35/si1 p30/uck1 p31/uo1 p32/ui1 p42/ui2 p41/uo2 p40/uck2 n-ch open-drain i/o port 10-bit a/d converter av cc, av ss , avr 3 p60/an0 to p67/an7 8 8 external interrupt p72/int2 p71/int1 p70/int0 n-ch open-drain output port 2 main clock oscillator x0 x1 port0 and port1 port 2 internal data bus 8-bit serial i/o port 3 port 4 uart baud rate generator port 5 port 6 port 7
mb89630r series 21 n cpu core 1. memory space the microcontrollers of the mb89630r series offer 64 kbytes of memory for storing all of i/o, data, and program areas. the i/o area is located at the lowest address. the data area is provided immediately above the i/o area. the data area can be divided into register, stack, and direct areas according to the application. the program area is located at exactly the opposite end of i/o area, that is, near the highest address. provide the tables of interrupt reset vectors and vector call instructions toward the highest address within the program area. the memory space of the mb89630r series is structured as illustrated below. ? memory space *1: the rom area is an external area depending on the mode. the internal rom cannot be used on the mb89t635r and mb89t637r. *2: addresses 8000 h to 8006 h for the mb89p637 and mb89w637 comprise an option area, do not use this area for the mb89pv630 and mb89637r. 0000 h 0080 h 0100 h 0480 h 8000 h 8007 h mb89pv630 i/o ram 1 kb register external area external rom 32 kb 0000 h 0080 h 0100 h 0200 h c000 h ffff h mb89635r mb89t635r i/o ram 512 b register rom* 1 16 kb 0000 h 0080 h 0100 h 0200 h a000 h mb89636r i/o ram 768 b register rom* 1 24 kb 0000 h 0080 h 0100 h 0200 h 8000 h 8007 h mb89637r mb89t637r mb89p637 mb89w637 i/o ram 1024 kb register rom* 1 32 kb ffff h external area external area external area *2 0380 h 0280 h 0200 h *2 0480 h ffff h ffff h *3 *3 0480 h 8000 h *3: the access is forbidden in the external bus mode.
mb89630r series 22 2. registers the f 2 mc-8l family has two types of registers; dedicated registers in the cpu and general-purpose registers in the memory. the following dedicated registers are provided: program counter (pc): a 16-bit register for indicating the instruction storage positions accumulator (a): a 16-bit temporary register for storing arithmetic operations, etc. when the instruction is an 8-bit data processing instruction, the lower byte is used. temporary accumulator (t): a16-bit register which performs arithmetic operations with the accumulator when the instruction is an 8-bit data processing instruction, the lower byte is used. index register (ix): a16-bit register for index modification extra pointer (ep): a16-bit pointer for indicating a memory address stack pointer (sp): a16-bit register for indicating a stack area program status (ps): a16-bit register for storing a register pointer, a condition code the ps can further be divided into higher 8 bits for use as a register bank pointer (rp) and the lower 8 bits for use as a condition code register (ccr). (see the diagram below.) pc a t ix ep sp ps 16 bits : program counter : accumulator : temporary accumulator : index register : extra pointer : stack pointer : program status fffd h i-flag = 0, il1, il0 = 11 the other bit values are indeterminate. initial value indeterminate indeterminate indeterminate indeterminate indeterminate indeterminate ? structure of the program status register vacancy vacancy vacancy h i il1, il0 n z vc 54 rp ps 109876 3210 15 14 13 12 11 rp ccr
mb89630r series 23 the rp indicates the address of the register bank currently in use. the relationship between the pointer contents and the actual address is based on the conversion rule illustrated below. the ccr consists of bits indicating the results of arithmetic operations and the contents of transfer data and bits for control of cpu operations at the time of an interrupt. h-flag: set to 1 when a carry or a borrow from bit 3 to bit 4 occurs as a result of an arithmetic operation. cleared to 0 otherwise. this flag is for decimal adjustment instructions. i-flag: interrupt is enabled when this flag is set to 1. interrupt is disabled when the flag is cleared to 0. cleared to 0 at the reset. il1, il0: indicates the level of the interrupt currently allowed. processes an interrupt only if its request level is higher than the value indicated by this bit. n-flag: set to 1 if the msb becomes to 1 as the result of an arithmetic operation. cleared to 0 when the bit is cleared to 0. z-flag: set to 1 when an arithmetic operation results in 0. cleared to 0 otherwise. v-flag: set to 1 if the complement on 2 overflows as a result of an arithmetic operation. cleared to 0 if the overflow doesnot occur. c-flag: set to 1 when a carry or a borrow from bit 7 occurs as a result of an arithmetic operation. cleared to 0 otherwise. set to the shift-out value in the case of a shift instruction. il1 il0 interrupt level high-low 00 1 high low 01 10 2 11 3 ? rule for conversion of actual addresses of the general-purpose register area ? a15 ? a14 ? a13 ? a12 ? a11 ? a10 ? a9 ? a8 r4 a7 r3 a6 r2 a5 r1 a4 r0 a3 b2 a2 b1 a1 b0 a0 lower op codes rp generated addresses
mb89630r series 24 the following general-purpose registers are provided: general-purpose registers: an 8-bit register for storing data the general-purpose registers are 8 bits and located in the register banks of the memory. one bank contains eight registers and up to a total of 32 banks can be used on the mb89653a (ram 512 8 bits). the bank currently in use is indicated by the register bank pointer (rp). ? register bank configuraiton this address = 0100 h + 8 (rp) memor y area 32 banks r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7
mb89630r series 25 n i/o map (continued) address read/write register name register description 00 h (r/w) pdr0 port 0 data register 01 h (w) ddr0 port 0 data direction register 02 h (r/w) pdr1 port 1 data register 03 h (w) ddr1 port 1 data direction register 04 h (r/w) pdr2 port 2 data register 05 h (w) bctr external bus pin control register 06 h vacancy 07 h (r/w) sycc system clock control register 08 h (r/w) stbc system clock control register 09 h (r/w) wdte watchdog timer control register 0a h (r/w) tbcr timebase timer control register 0b h (r/w) wpcr watch prescaler control register 0c h (r/w) chg3 port 3 switching register 0d h (r/w) pdr3 port 3 data register 0e h (w) ddr3 port 3 data direction register 0f h (r/w) pdr4 port 4 data register 10 h (w) ddr4 port 4 data direction register 11 h (r/w) buzr buzzer register 12 h (r/w) pdr5 port 5 data register 13 h (r/w) pdr6 port 6 data register 14 h (r) pdr7 port 7 data register 15 h (r/w) pcr1 pwc pulse width control register 1 16 h (r/w) pcr2 pwc pulse width control register 2 17 h (r/w) rlbr pwc reload buffer register 18 h (r/w) tmcr 16-bit timer control register 19 h (r/w) tchr 16-bit timer count register (h) 1a h (r/w) tclr 16-bit timer count register (l) 1b h vacancy 1c h (r/w) smr1 serial mode register 1d h (r/w) sdr1 serial data register 1e h vacancy 1f h vacancy
mb89630r series 26 (continued) note: do not use vacancies. address read/write register name register description 20 h (r/w) adc1 a/d converter control register 1 21 h (r/w) adc2 a/d converter control register 2 22 h (r/w) addh a/d converter data register (h) 23 h (r/w) addl a/d converter data register (l) 24 h (r/w) eic1 external interrupt control register 1 25 h (r/w) eic2 external interrupt control register 2 26 h vacancy 27 h vacancy 28 h (r/w) cntr1 pwm timer control register 1 29 h (r/w) cntr2 pwm timer control register 2 2a h (r/w) cntr3 pwm timer control register 3 2b h (w) comr1 pwm timer compare register 1 2c h (w) comr2 pwm timer compare register 2 2d h (r/w) smc uart serial mode control register 2e h (r/w) src uart serial rate control register 2f h (r/w) ssd uart serial status/data register 30 h (r) (w) sidr sodr uart serial input data control register uart serial output data control register 31 h to 7b h vacancy 7c h (w) ilr1 interrupt level setting register 1 7d h (w) ilr2 interrupt level settingregister 2 7e h (w) ilr3 interrupt level setting register 3 7f h vacancy
mb89630r series 27 n electrical characteristics 1. absolute maximum ratings (av ss = v ss = 0.0 v) * : use av cc and v cc set at the same voltage. take care so that av cc does not exceed v cc , such as when power is turned on. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol value unit remarks min. max. power supply voltage v cc v ss C 0.3 v ss + 7.0 v * av cc v ss C 0.3 v ss + 7.0 v * a/d converter reference input voltage avr v ss C 0.3 v ss + 7.0 v avr must not exceed av cc + 0.3 v. input voltage v i v ss C 0.3 v cc + 0.3 v except p50 to p53 v i2 v ss C 0.3 v ss + 7.0 v p50 to p53 output voltage v o v ss C 0.3 v cc + 0.3 v except p50 to p53 v o2 v ss C 0.3 v ss + 7.0 v p50 to p53 l level maximum output current i ol ? 20 ma l level average output current i olav ? 4ma average value (operating current operating rate) l level total maximum output current ? i ol ? 100 ma l level total average output current ? i olav ? 40 ma average value (operating current operating rate) h level maximum output current i oh ? C20 ma h level average output current i ohav ? C4 ma average value (operating current operating rate) h level total maximum output current ? i oh ? C50 ma h level total average output current ? i ohav ? C20 ma average value (operating current operating rate) power consumption p d ? 500 mw operating temperature t a C40 +85 c storage temperature tstg C55 +150 c
mb89630r series 28 2. recommended operating conditions (av ss = v ss = 0.0 v) * : these values vary with the operating frequency, instruction cycle, and analog assurance range. see figure 1 and 5. a/d converter electrical characteristics. figure 1 indicates the operating frequency of the external oscillator at an instruction cycle of 4/f ch . since the operating voltage range is dependent on the instruction cycle, see minimum execution time if the operating speed is switched using a gear. parameter symbol value unit remarks min. max power supply voltage v cc 2.2* 6.0* v normal operation assurance range* mb89635r/637r 2.7* 6.0* v normal operation assurance range* mb89pv630/p637/ w637/t635r/t637r av cc 1.5 6.0 v retains the ram state in stop mode a/d converter reference input voltage avr 3.0 av cc v operating temperature t a C40 +85 c 6 5 4 3 2 1 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 4.0 2.0 0.8 0.4 minimum execution time (instruction cycle) ( m s) main clock operating frequency (at an instruction cycle of 4/f ch ) (mhz) operation assurance range analog accuracy assured in the av cc = 3.5 v to 6.0 v range operating voltage (v) note: the shaded area is assured only for the mb89635r/636r/637r. figure 1 operating voltage vs. main clock operating frequency
mb89630r series 29 warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand.
mb89630r series 30 3. dc characteristics (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. h level input voltage v ih1 p00 to p07, p10 to p17, p22, p23, p31, p34, p37, p41, p43, p51 to p53 ? 0.7 v cc ? v cc + 0.3 v p51 to p53 with pull-up resistor v ih2 p51 to p53 0.7 v cc ? v ss + 6.0 v without pull-up resistor v ihs rst , mod0, mod1, p30, p32, p33, p35, p36, p40, p42,p50, p72 to p74 0.8 v cc ? v cc + 0.3 v p50 with pull-up resistor v ihs2 p50, p70, p71 0.8 v cc ? v ss + 6.0 v without pull-up resistor l level input voltage v il p00 to p07, p10 to p17, p22, p23, p31, p34, p37, p41, p43 v ss - 0.3 ? 0.3 v cc v v ils p30, p32, p33, p35, p36, p40, p42, p50 to p53, p70 to p74, rst , mod0, mod1 v ss - 0.3 ? 0.2 v cc v open-drain output pin application voltage v d p50 to p53 v ss - 0.3 ? v ss + 6.0 v h level output voltage v oh p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p43 i oh = C2.0 ma 4.0 ?? v l level output voltage v ol p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p43, p50 to p53, p60 to p67, rst i ol = 4.0 ma ?? 0.4 v input leakage current (hi-z output leakage current) i li p00 to p07, p10 to p17, p20 to p23, p30 to p37, p40 to p43, p50 to p53, p70 to p74, mod0, mod1 0.0 v < v i < v cc ?? 5 m a without pull-up resistor
mb89630r series 31 (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) (continued) parameter symbol pin name condition value unit remarks min. typ. max. pull-up resistance r pull p00 to p07, p10 to p17, p30 to p37, p40 to p43, p50 to p53, p72 to p74 v i = 0.0 v 25 50 100 k w with pull-up resistor power supply current *1 i cc1 v cc f ch = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 1220ma i cc2 f ch = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 1.0 2ma mb89635r/t635r/ 636r/637r/t637r/ pv630 1.52.5ma mb89p637/w637 i ccs1 f ch = 10 mhz v cc = 5.0 v t inst *2 = 0.4 m s 3 7ma i ccs2 f ch = 10 mhz v cc = 3.0 v t inst *2 = 6.4 m s 0.51.5ma i ccl f cl = 32.768 khz, v cc = 3.0 v subclock mode 50100 m a mb89635r/t635r/ 636r/637r/t637r/ pv630 500700 m a mb89p637/w637 i ccls f cl = 32.768 khz, v cc = 3.0 v subclock sleep mode 2550 m a i cct f cl = 32.768 khz, v cc = 3.0 v ?watch mode ? main clock stop mode at dual- clock system 315 m a i cch t a = +25 c ? subclock stop mode ? main clock stop mode at single- clock system 1 m a sleep mode
mb89630r series 32 (continued) (av cc = v cc = 5.0 v, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: the power supply current is measured at the external clock. in the case of the mb89pv630, the current consumed by the connected eprom and ice is not counted. *2: for information on t inst , see (4) instruction cycle in 4. ac characteristics. 4. ac characteristics (1) reset timing (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name condition value unit remarks min. typ. max. power supply current *1 i a av cc f ch = 10 mhz, when a/d conversion operates. 6ma i ah f ch = 10 mhz, t a = +25 c, when a/d conversion in a stop. 1 m a input capacitance c in other than av cc , av ss , v cc , and v ss f = 1 mhz 10 pf parameter symbol condition value unit remarks min. max. rst l pulse width t zlzh 48 t hcyl ns t zlzh 0.2 v cc 0.2 v cc rst
mb89630r series 33 (2) specification for power-on reset (av ss = v ss = 0.0 v, t a = C40 c to +85 c) note: make sure that power supply rises within the selected oscillation stabilization time. if power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. (3) clock timing (av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol condition value unit remarks min. max. power supply rising time t r 50 ms power-on reset function only power supply cut-off time t off 1ms min. interval time for the next power-on reset parameter symbol pin name condition value unit remarks min. typ. max. clock frequency f ch x0, x1 110mhz f cl x0a, x1a 32.768 khz clock cycle time t hcyl x0, x1 100 1000 ns t lcyl x0a, x1a 30.5 m s input clock pulse width p wh p wl x0 20 ns external clock p wlh p wll x0a 15.2 m s external clock input clock rising/falling time t cr t cf x0 10 ns external clock 0.2 v 0.2 v 2.0 v 0.2 v t r v cc t off
mb89630r series 34 0.2 v cc 0.8 v cc x0 0.2 v cc t cr p wh t cf 0.8 v cc 0.2 v cc x0 x1 x0 x1 when a crystal or ceramic reasonator is used when an external clock is used open t hcyl p wl ? main clock timing condition ? main clock configurations x0a x0a x1a x0a x1a open 0.2 v cc 0.8 v cc 0.2 v cc t cr t cf 0.8 v cc 0.2 v cc t lcyl p wlh p wll when a crystal or ceramic reasonator is used when an external clock is used ? subclock timing condition ? subclock configurations
mb89630r series 35 (4) instruction cycle note: operating at 10 mhz, the cycle varies with the set execution time. (5) clock output timing (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol value (typical) unit remarks instruction cycle (minimum execution time) t inst 4/f ch , 8/f ch , 16/f ch , 64/f ch m s (4/f ch ) t inst = 0.4 m s, operating at f ch = 10 mhz 2/f cl m s t inst = 61.036 m s, operating at f cl = 32.768 khz parameter symbol pin name condition value unit remarks min. max. clock time t cyc clk 1/2 t inst * m s clk - ? clk t chcl clk 1/4 t inst * C 70 ns 1/4 t inst * m s clk 2.4 v 2.4 v 0.8 v t cyc t chcl
mb89630r series 36 (6) bus read timing (v cc = 5.0 v 10%, 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition value unit remarks min. max. valid address ? rd time t avrl rd , a15 to a08, ad7 to ad0 1/4 t inst *C 64 ns m s rd pulse width t rlrh rd 1/2 t inst *C 20 ns m s valid address ? data read time t avdv ad7 to ad0, a15 to a08 1/2 t inst *200 m sno wait rd ? data read time t rldv rd , ad7 to ad0 1/2 t inst *C 80 ns 120 m sno wait rd - ? data hold time t rhdx ad7 to ad0, rd 0 m s rd - ? ale - time t rhlh rd , ale 1/4 t inst *C 40 ns m s rd - ? address loss time t rhax rd , a15 to a08 1/4 t inst *C 40 ns m s rd ? clk - time t rlch rd , clk 1/4 t inst *C 40 ns m s clk ? rd - time t clrh 0ns rd ? bufc time t rlbl rd , bufc C5 m s bufc - ? valid address time t bhav a15 to a08, ad7 to ad0, bufc 5 m s bufc a ad ale clk rd 0.8 v 0.8 v 0.8 v 0.8 v 2.4 v 2.4 v 0.8v 2.4v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.3 v cc 0.7 v cc 0.3 v cc 0.7 v cc t rhdx t clrh t rlbl t bhav t rhlh t avdv t rlch t rhax t rldv t rlrh t avrl
mb89630r series 37 (7) bus write timing (v cc = 5.0 v 10%, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) *1: for information on t inst , see (4) instruction cycle. *2: this characteristics are also applicable to the bus read timing. parameter symbol pin name condition value unit remarks min. max. valid address ? ale time t avll ad7 to ad0, ale a15 to a08 1/4 t inst * 1 C 64 ns* 2 m s ale time ? address loss time t llax 5ns valid address ? wr time t avwl wr , ale 1/4 t inst * 1 C 60 ns* 2 m s wr pulse width t wlwh wr 1/2 t inst * 1 C 20 ns* 2 m s write data ? wr - time t dvwh ad7 to ad0, wr 1/2 t inst * 1 C 60 ns* 2 m s wr - ? address loss time t whax wr , a15 to a08 1/4 t inst * 1 C 40 ns* 2 m s wr - ? data hold time t whdx ad7 to ad0, wr 1/4 t inst * 1 C 40 ns* 2 m s wr - ? ale - time t whlh wr , ale 1/4 t inst * 1 C 40 ns* 2 m s wr ? clk - time t wlch wr , clk 1/4 t inst * 1 C 40 ns* 2 m s clk ? wr - time t clwh 0ns ale pulse width t lhll ale 1/4 t inst * 1 C 35 ns* 2 m s ale ? clk - time t llch ale,clk 1/4 t inst * 1 C 30 ns* 2 m s a ad ale clk wr 0.8v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v t clwh 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v 2.4 v t llax t lhll t llch t avll t dvwh t whdx t whax t wlch t avwl t whlh t wlwh
mb89630r series 38 (8) ready input timing (v cc = 5.0 v 10%, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : this characteristics are also applicable to the read cycle. parameter symbol pin name condition value unit remarks min. max. rdy valid ? clk - time t yvch rdy, clk 60 ns * clk - ? rdy loss time t chyx 0ns* a ad ale clk wr rdy 2.4 v 2.4 v t yvch t chyx t yvch t chyx address data note: the bus cycle is also extended in the read cycle in the same manner.
mb89630r series 39 (9) serial i/o timing (v cc = 5.0 v 10%, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst , see (4) instruction cycle. parameter symbol pin name condition value unit remarks min. max. serial clock cycle time t scyc sck1, uck1, uck2 internal shift clock mode 2 t inst * m s sck1 ? so1 time uck1 ? uo1 time uck2 ? uo2 time t slov sck1, so1 uck1, uo1 uck2, uo2 C200 200 ns valid si1 ? sck1 - valid ui1 ? uck1 - valid ui2 ? uck2 - t ivsh si1, sck1 ui1, uck1 ui2, uck2 1/2 t inst * m s sck1 - ? valid si1 hold time uck1 - ? valid ui1 hold time uck2 - ? valid ui2 hold time t shix sck1, si1 uck1, ui1 uck2, ui2 1/2 t inst * m s serial clock h pulse width t shsl sck1, uck1, uck2 external shift clock mode 1 t inst * m s serial clock l pulse width t slsh sck1, uck1, uck2 1 t inst * m s sck1 ? so1 time uck1 ? uo1 time uck2 ? uo2 time t slov sck1, so1 uck1, uo1 uck2, uo2 0 200 ns valid si1 ? sck1 - valid ui1 ? uck1 - valid ui2 ? uck2 - t ivsh si1, sck1 ui1, uck1 ui2, uck2 1/2 t inst * m s sck1 ? valid si1 hold time uck1 ? valid ui1 hold time uck2 ? valid ui2 hold time t shix sck1, si1 uck1, ui1 uck2, ui2 1/2 t inst * m s
mb89630r series 40 2.4 v 0.8 v 0.8 v t slov 0.8 v 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc si1 ui1 ui sck1 uck1 uck2 0.8 v cc 0.2 v cc 0.8 v cc t slov 0.8 v 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t scyc t ivsh t shix t slsh t shsl t ivsh t shix so1 uo1 uo2 si1 ui1 ui sck1 uck1 uck2 so1 uo1 uo2 ? internal shift clock mode ? external shift clock mode
mb89630r series 41 (10) peripheral input timing (v cc = 5.0 v 10%, av ss = v ss = 0.0 v, t a = C40 c to +85 c) * : for information on t inst, see (4) instruction cycle. parameter symbol pin name value unit remarks min. max. peripheral input h pulse width 1 t ilih1 pwc, int0 to int3,ec 2 t inst * m s peripheral input l pulse width 1 t ihil1 2 t inst * m s peripheral input h pulse width 2 t ilih2 adst 2 8 t inst * m s a/d mode peripheral input l pulse width 2 t ihil2 2 8 t inst * m s a/d mode peripheral input h pulse width 3 t ilih3 adst 2 8 t inst * m ssense mode peripheral input l pulse width 3 t ihil3 2 8 t inst * m ssense mode 0.2 v cc 0.8 v cc t ihil1 pwc, ec, int0 to int3 0.2 v cc t ilih1 adst 0.8 v cc 0.2 v cc 0.8 v cc t ihil2 (t ihil3 ) 0.2 v cc t ilih2 (t ilih3 ) 0.8 v cc
mb89630r series 42 5. a/d converter electrical characteristics (av cc = v cc = 3.5 v to 6.0 v, f ch = 10 mhz, av ss = v ss = 0.0 v, t a = C40 c to +85 c) parameter symbol pin name value unit remarks min. typ. max. resolution 10bit at av cc = v cc linearity error 2.0 lsb differential linearity error 1.5 lsb total error 3.0 lsb zero transition voltage v ot an0 to an7 av ss C 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb mv full-scale transition voltage v fst avr C 3.5 lsb avr C 1.5 lsb avr + 0.5 lsb mv interchannel disparity 4lsb a/d mode conversion time 13.2 m s at 10 mhz oscillation analog port input current i ain an0 to an7 10 m a analog input voltage 0.0 avr v reference voltage 0.0 av cc v reference voltage supply current i r 200 ?m a avr = 5.0 v
mb89630r series 43 6. a/d converter glossary ? resolution analog changes that are identifiable with the a/d converter ? linearity error the deviation of the straight line connecting the zero transition point (00 0000 0000 ? 00 0000 0001) with the full-scale transition point (11 1111 1110 ? 11 1111 1111) from actual conversion characteristics ? differential linearity error the deviation of input voltage needed to change the output code by 1 lsb from the theoretical value ? total error (unit: lsb) the difference between theoretical and actual conversion values caused by the zero transition error, full-scale transition error, linearity error, quantization error, and noise (continued) 0.5 lsb 1 lsb analog input av ss 1.5 lsb theoretical i/o characteristics 3ff 3fe 3fd 004 003 002 001 avr theoretical value analog input av ss v nt actual conversion value total error 3ff 3fe 3fd 004 003 002 001 avr {1 lsb n + 0.5 lsb} v fst v ot actual conversion value digital output n total error = v nt ?{1 lsb n + 0.5 lsb} 1 lsb 1 lsb = v fst ? ot 1022 digital output digital output (v)
mb89630r series 44 (continued) analog input av ss linearity error 3ff 3fe 3fd 004 003 002 001 avr theoretical value analog input av ss v nt v (n + 1)t actual conversion value differential linearity error n + 1 n n ?1 n ?2 avr v nt v ot (actual measurement) actual conversion value actual conversion value digital output n differential linearity error = 1 lsb v (n + 1)t ? nt digital output digital output digital output n linearity error = v nt {1 lsb n + v ot } 1 lsb ?1 {1 lsb n + v ot } actual conversion value v fst (actual measurement) theoretical value analog input av ss zero transition error 004 003 002 001 theoretical value analog input actual conversion value full-scale transition error avr actual conversion value digital output digital output actual conversion value actual conversion value v ot (actual measurement) v fst (actual measurement) 3ff 3fe 3fd 3fc
mb89630r series 45 7. notes on using a/d converter ? input impedance of the analog input pins the output impedance of the external circuit for the analog input must satisfy the followingconditions. if the output impedance of the external circuit is too high, an analog voltage sampling time might beinsufficient (sampling time = 6 m s at 10mhz oscillation.) therefore, it is recommended to keep the output impedance of the external circuit below 10 k w . ?error the smaller the | avrCavss |, the greater the error would become relatively. analog input circuit model analog input note: the values mentioned here should be used as a guideline. r on1 : r on2 : c 0 : c 1 : converter c 0 c 1 r on2 r on1 approx. 1.5 k w approx. 1.5 k w approx. 60 pf approx. 4 pf
mb89630r series 46 n characteristics example (1) l level output voltage (2) h level output voltage (3) h level input voltage/l level input (4) h level input voltage/l level input voltage (cmos input) voltage (hysteresis input) v ihs : threshold as the input voltage in hysteresis v ils : threshold as the input voltage in hysteresis characteristics is set to h level characteristics is set to l level 010 123456789 0.1 0.2 0.3 0.4 0.5 v ol (v) v cc = 4.0 v v cc = 3.0 v v cc = 5.0 v v cc = 6.0 v i ol (ma) v ol vs. i ol t a = +25 c 0.0 1.0 v cc - v oh (v) v cc = 2.5 v v cc = 3.0 v v cc = 4.0 v v cc = 5.0 v v cc = 6.0 v i oh (ma) v cc - v oh vs. i oh 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 ?.5 ?.0 ?.5 ?.0 ?.5 ?.0 t a = +25 c 012 3 456 7 v cc (v) 5.0 v in (v) v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 t a = +25 c 012 3 456 7 v cc (v) 5.0 v in (v) v in vs. v cc 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 v ihs v ils t a = +25 c
mb89630r series 47 (continued) (5) power supply current (external clock) i cc (ma) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 2 4 6 8 10 12 14 16 divide by 8 divide by 16 divide by 64 (i cc2 ) t a = +25 c f ch = 10mhz i cc1 vs. v cc , i cc2 vs. v cc i ccs (ma) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 divide by 8 divide by 16 divide by 64 (i ccs2 ) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 t a = +25 c f ch = 10mhz i ccs1 vs. v cc , i ccs2 vs. v cc i ccl ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 20 40 60 80 100 120 140 160 180 200 t a = +25 c i ccl vs. v cc i ccls ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 5 10 15 20 25 30 35 40 45 50 t a = +25 c i ccls vs. v cc divide by 4 (i cc1 ) divide by 4 (i ccs1 )
mb89630r series 48 (continued) (6) pull-up resistance i cct ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 2 4 6 8 10 12 14 16 18 20 t a = +25 c i cct vs. v cc i cch ( m a) v cc (v) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 t a = +25 c i cch vs. v cc r pull vs. v cc 234 5 6 r pull (k w ) 10 1 100 1000 t a = +25 c v cc (v)
mb89630r series 49 n instructions (136 instructions) execution instructions can be divided into the following four groups: ? transfer ? arithmetic operation ? branch ?others table 1 lists symbols used for notation of instructions. table 1 instruction symbols columns indicate the following: mnemonic: assembler notation of an instruction ~: the number of instructions #: the number of bytes operation: operation of an instruction tl, th, ah: a content change when each of the tl, th, and ah instructions is executed. symbols in the column indicate the following: ? C indicates no change. ? dh is the 8 upper bits of operation description data. ? al and ah must become the contents of al and ah prior to the instruction executed. ? 00 becomes 00. n, z, v, c: an instruction of which the corresponding flag will change. if + is written in this column, the relevant instruction will change its corresponding flag. op code: code of an instruction. if an instruction is more than one code, it is written according to the following rule: example: 48 to 4f ? this indicates 48, 49, ... 4f. symbol meaning dir direct address (8 bits) off offset (8 bits) ext extended address (16 bits) #vct vector table number (3 bits) #d8 immediate data (8 bits) #d16 immediate data (16 bits) dir: b bit direct address (8:3 bits) rel branch relative address (8 bits) @ register indirect (example: @a, @ix, @ep) a accumulator a (whether its length is 8 or 16 bits is determined by the instruction in use.) ah upper 8 bits of accumulator a (8 bits) al lower 8 bits of accumulator a (8 bits) t temporary accumulator t (whether its length is 8 or 16 bits is determined by the instruction in use.) th upper 8 bits of temporary accumulator t (8 bits) tl lower 8 bits of temporary accumulator t (8 bits) ix index register ix (16 bits) ep extra pointer ep (16 bits) pc program counter pc (16 bits) sp stack pointer sp (16 bits) ps program status ps (16 bits) dr accumulator a or index register ix (16 bits) ccr condition code register ccr (8 bits) rp register bank pointer rp (5 bits) ri general-purpose register ri (8 bits, i = 0 to 7) indicates that the very is the immediate data. (whether its length is 8 or 16 bits is determined by the instruction in use.) ( ) indicates that the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.) (( )) the address indicated by the contents of is the target of accessing. (whether its length is 8 or 16 bits is determined by the instruction in use.)
mb89630r series 50 table 2 transfer instructions (48 instructions) note: during byte transfer to a, t ? a is restricted to low bytes. operands in more than one operand instruction must be stored in the order in which their mnemonics are written. (reverse arrangement of f 2 mc-8 family) mnemonic ~ # operation tl th ah n z v c op code mov dir,a mov @ix +off,a mov ext,a mov @ep,a mov ri,a mov a,#d8 mov a,dir mov a,@ix +off mov a,ext mov a,@a mov a,@ep mov a,ri mov dir,#d8 mov @ix +off,#d8 mov @ep,#d8 mov ri,#d8 movw dir,a movw @ix +off,a movw ext,a movw @ep,a movw ep,a movw a,#d16 movw a,dir movw a,@ix +off movw a,ext movw a,@a movw a,@ep movw a,ep movw ep,#d16 movw ix,a movw a,ix movw sp,a movw a,sp mov @a,t movw @a,t movw ix,#d16 movw a,ps movw ps,a movw sp,#d16 swap setb dir: b clrb dir: b xch a,t xchw a,t xchw a,ep xchw a,ix xchw a,sp movw a,pc 3 4 4 3 3 2 3 4 4 3 3 3 4 5 4 4 4 5 5 4 2 3 4 5 5 4 4 2 3 2 2 2 2 3 4 3 2 2 3 2 4 4 2 3 3 3 3 2 2 2 3 1 1 2 2 2 3 1 1 1 3 3 2 2 2 2 3 1 1 3 2 2 3 1 1 1 3 1 1 1 1 1 1 3 1 1 3 1 2 2 1 1 1 1 1 1 (dir) ? (a) ( (ix) +off ) ? (a) (ext) ? (a) ( (ep) ) ? (a) (ri) ? (a) (a) ? d8 (a) ? (dir) (a) ? ( (ix) +off) (a) ? (ext) (a) ? ( (a) ) (a) ? ( (ep) ) (a) ? (ri) (dir) ? d8 ( (ix) +off ) ? d8 ( (ep) ) ? d8 (ri) ? d8 (dir) ? (ah),(dir + 1) ? (al) ( (ix) +off) ? (ah), ( (ix) +off + 1) ? (al) (ext) ? (ah), (ext + 1) ? (al) ( (ep) ) ? (ah),( (ep) + 1) ? (al) (ep) ? (a) (a) ? d16 (ah) ? (dir), (al) ? (dir + 1) (ah) ? ( (ix) +off), (al) ? ( (ix) +off + 1) (ah) ? (ext), (al) ? (ext + 1) (ah) ? ( (a) ), (al) ? ( (a) ) + 1) (ah) ? ( (ep) ), (al) ? ( (ep) + 1) (a) ? (ep) (ep) ? d16 (ix) ? (a) (a) ? (ix) (sp) ? (a) (a) ? (sp) ( (a) ) ? (t) ( (a) ) ? (th),( (a) + 1) ? (tl) (ix) ? d16 (a) ? (ps) (ps) ? (a) (sp) ? d16 (ah) ? (al) (dir): b ? 1 (dir): b ? 0 (al) ? (tl) (a) ? (t) (a) ? (ep) (a) ? (ix) (a) ? (sp) (a) ? (pc) C C C C C al al al al al al al C C C C C C C C C al al al al al al C C C C C C C C C C C C C C C al al C C C C C C C C C C C C C C C C C C C C C C C C C ah ah ah ah ah ah C C C C C C C C C C C C C C C C ah C C C C C C C C C C C C C C C C C C C C C C C C C dh dh dh dh dh dh dh C C dh C dh C C C dh C C al C C C dh dh dh dh dh C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + C C + + C C + + C C + + C C + + C C + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + + + C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 45 46 61 47 48 to 4f 04 05 06 60 92 07 08 to 0f 85 86 87 88 to 8f d5 d6 d4 d7 e3 e4 c5 c6 c4 93 c7 f3 e7 e2 f2 e1 f1 82 83 e6 70 71 e5 10 a8 to af a0 to a7 42 43 f7 f6 f5 f0
mb89630r series 51 table 3 arithmetic operation instructions (62 instructions) (continued) mnemonic ~ # operation tl th ah n z v c op code addc a,ri addc a,#d8 addc a,dir addc a,@ix +off addc a,@ep addcw a addc a subc a,ri subc a,#d8 subc a,dir subc a,@ix +off subc a,@ep subcw a subc a inc ri incw ep incw ix incw a dec ri decw ep decw ix decw a mulu a divu a andw a orw a xorw a cmp a cmpw a rorc a rolc a cmp a,#d8 cmp a,dir cmp a,@ep cmp a,@ix +off cmp a,ri daa das xor a xor a,#d8 xor a,dir xor a,@ep xor a,@ix +off xor a,ri and a and a,#d8 and a,dir 3 2 3 4 3 3 2 3 2 3 4 3 3 2 4 3 3 3 4 3 3 3 19 21 3 3 3 2 3 2 2 2 3 3 4 3 2 2 2 2 3 3 4 3 2 2 3 1 2 2 2 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 2 1 1 1 1 2 2 1 2 1 1 2 2 (a) ? (a) + (ri) + c (a) ? (a) + d8 + c (a) ? (a) + (dir) + c (a) ? (a) + ( (ix) +off) + c (a) ? (a) + ( (ep) ) + c (a) ? (a) + (t) + c (al) ? (al) + (tl) + c (a) ? (a) - (ri) - c (a) ? (a) - d8 - c (a) ? (a) - (dir) - c (a) ? (a) - ( (ix) +off) - c (a) ? (a) - ( (ep) ) - c (a) ? (t) - (a) - c (al) ? (tl) - (al) - c (ri) ? (ri) + 1 (ep) ? (ep) + 1 (ix) ? (ix) + 1 (a) ? (a) + 1 (ri) ? (ri) - 1 (ep) ? (ep) - 1 (ix) ? (ix) - 1 (a) ? (a) - 1 (a) ? (al) (tl) (a) ? (t) / (al),mod ? (t) (a) ? (a) (t) (a) ? (a) (t) (a) ? (a) " (t) (tl) - (al) (t) - (a) (a) - d8 (a) - (dir) (a) - ( (ep) ) (a) - ( (ix) +off) (a) - (ri) decimal adjust for addition decimal adjust for subtraction (a) ? (al) " (tl) (a) ? (al) " d8 (a) ? (al) " (dir) (a) ? (al) " ( (ep) ) (a) ? (al) " ( (ix) +off) (a) ? (al) " (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) C C C C C C C C C C C C C C C C C C C C C C C dl C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C 00 C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C dh C C C C dh C C C dh dh 00 dh dh dh C C C C C C C C C C C C C C C C C C C C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + C C C C C C C C C + + C C + + + C C C C C C C C C + + C C C C C C C C C C + + r C + + r C + + r C + + + + + + + + + + C + + + C + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C 28 to 2f 24 25 26 27 23 22 38 to 3f 34 35 36 37 33 32 c8 to cf c3 c2 c0 d8 to df d3 d2 d0 01 11 63 73 53 12 13 03 02 14 15 17 16 18 to 1f 84 94 52 54 55 57 56 58 to 5f 62 64 65 a c ? ? ?? a c
mb89630r series 52 (continued) table 4 branch instructions (17 instructions) table 5 other instructions (9 instructions) mnemonic ~ # operation tl th ah n z v c op code and a,@ep and a,@ix +off and a,ri or a or a,#d8 or a,dir or a,@ep or a,@ix +off or a,ri cmp dir,#d8 cmp @ep,#d8 cmp @ix +off,#d8 cmp ri,#d8 incw sp decw sp 3 4 3 2 2 3 3 4 3 5 4 5 4 3 3 1 2 1 1 2 2 1 2 1 3 2 3 2 1 1 (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (a) ? (al) (tl) (a) ? (al) d8 (a) ? (al) (dir) (a) ? (al) ( (ep) ) (a) ? (al) ( (ix) +off) (a) ? (al) (ri) (dir) C d8 ( (ep) ) C d8 ( (ix) + off) C d8 (ri) C d8 (sp) ? (sp) + 1 (sp) ? (sp) C 1 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + r C + + + + + + + + + + + + + + + + C C C C C C C C 67 66 68 to 6f 72 74 75 77 76 78 to 7f 95 97 96 98 to 9f c1 d1 mnemonic ~ # operation tl th ah n z v c op code bz/beq rel bnz/bne rel bc/blo rel bnc/bhs rel bn rel bp rel blt rel bge rel bbc dir: b,rel bbs dir: b,rel jmp @a jmp ext callv #vct call ext xchw a,pc ret reti 3 3 3 3 3 3 3 3 5 5 2 3 6 6 3 4 6 2 2 2 2 2 2 2 2 3 3 1 3 1 3 1 1 1 if z = 1 then pc ? pc + rel if z = 0 then pc ? pc + rel if c = 1 then pc ? pc + rel if c = 0 then pc ? pc + rel if n = 1 then pc ? pc + rel if n = 0 then pc ? pc + rel if v " n = 1 then pc ? pc + rel if v " n = 0 then pc ? pc + rei if (dir: b) = 0 then pc ? pc + rel if (dir: b) = 1 then pc ? pc + rel (pc) ? (a) (pc) ? ext vector call subroutine call (pc) ? (a),(a) ? (pc) + 1 return from subrountine return form interrupt C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C + C C C + C C C C C C C C C C C C C C C C C C C C C C C C C C restore fd fc f9 f8 fb fa ff fe b0 to b7 b8 to bf e0 21 e8 to ef 31 f4 20 30 mnemonic ~ # operation tl th ah n z v c op code pushw a popw a pushw ix popw ix nop clrc setc clri seti 4 4 4 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 C C C C C C C C C C C C C C C C C C C dh C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C r C C C s C C C C C C C C 40 50 41 51 00 81 91 80 90
mb89630r series 53 n instruction map h l 0123456789abcdef 0 nop swap ret reti pushw a popw a mov a,ext movw a,ps clri seti clrb dir: 0 bbc dir: 0,rel incw a decw a jmp @a movw a,pc 1 mulu a divu a jmp addr16 call addr16 pushw ix popw ix mov ext,a movw ps,a clrc setc clrb dir: 1 bbc dir: 1,rel incw sp decw sp movw sp,a movw a,sp 2 rolc a cmp a addc a subc a xch a, t xor a and a or a mov @a,t mov a,@a clrb dir: 2 bbc dir: 2,rel incw ix decw ix movw ix,a movw a,ix 3 rorc a cmpw a addcw a subcw a xchw a, t xorw a andw a orw a movw @a,t movw a,@a clrb dir: 3 bbc dir: 3,rel incw ep decw ep movw ep,a movw a,ep 4 mov a,#d8 cmp a,#d8 addc a,#d8 subc a,#d8 xor a,#d8 and a,#d8 or a,#d8 daa das clrb dir: 4 bbc dir: 4,rel movw a,ext movw ext,a movw a,#d16 xchw a,pc 5 mov a,dir cmp a,dir addc a,dir subc a,dir mov dir,a xor a,dir and a,dir or a,dir mov dir,#d8 cmp dir,#d8 clrb dir: 5 bbc dir: 5,rel movw a,dir movw dir,a movw sp,#d16 xchw a,sp 6 mov a,@ix +d cmp a,@ix +d addc a,@ix +d subc a,@ix +d mov @ix +d,a xor a,@ix +d and a,@ix +d or a,@ix +d mov @ix +d,#d8 cmp @ix +d,#d8 clrb dir: 6 bbc dir: 6,rel movw a,@ix +d movw @ix +d,a movw ix,#d16 xchw a,ix 7 mov a,@ep cmp a,@ep addc a,@ep subc a,@ep mov @ep,a xor a,@ep and a,@ep or a,@ep mov @ep,#d8 cmp @ep,#d8 clrb dir: 7 bbc dir: 7,rel movw a,@ep movw @ep,a movw ep,#d16 xchw a,ep 8 mov a,r0 cmp a,r0 addc a,r0 subc a,r0 mov r0,a xor a,r0 and a,r0 or a,r0 mov r0,#d8 cmp r0,#d8 setb dir: 0 bbs dir: 0,rel inc r0 dec r0 callv #0 bnc rel 9 mov a,r1 cmp a,r1 addc a,r1 subc a,r1 mov r1,a xor a,r1 and a,r1 or a,r1 mov r1,#d8 cmp r1,#d8 setb dir: 1 bbs dir: 1,rel inc r1 dec r1 callv #1 bc rel a mov a,r2 cmp a,r2 addc a,r2 subc a,r2 mov r2,a xor a,r2 and a,r2 or a,r2 mov r2,#d8 cmp r2,#d8 setb dir: 2 bbs dir: 2,rel inc r2 dec r2 callv #2 bp rel b mov a,r3 cmp a,r3 addc a,r3 subc a,r3 mov r3,a xor a,r3 and a,r3 or a,r3 mov r3,#d8 cmp r3,#d8 setb dir: 3 bbs dir: 3,rel inc r3 dec r3 callv #3 bn rel c mov a,r4 cmp a,r4 addc a,r4 subc a,r4 mov r4,a xor a,r4 and a,r4 or a,r4 mov r4,#d8 cmp r4,#d8 setb dir: 4 bbs dir: 4,rel inc r4 dec r4 callv #4 bnz rel d mov a,r5 cmp a,r5 addc a,r5 subc a,r5 mov r5,a xor a,r5 and a,r5 or a,r5 mov r5,#d8 cmp r5,#d8 setb dir: 5 bbs dir: 5,rel inc r5 dec r5 callv #5 bz rel e mov a,r6 cmp a,r6 addc a,r6 subc a,r6 mov r6,a xor a,r6 and a,r6 or a,r6 mov r6,#d8 cmp r6,#d8 setb dir: 6 bbs dir: 6,rel inc r6 dec r6 callv #6 bge rel f mov a,r7 cmp a,r7 addc a,r7 subc a,r7 mov r7,a xor a,r7 and a,r7 or a,r7 mov r7,#d8 cmp r7,#d8 setb dir: 7 bbs dir: 7,rel inc r7 dec r7 callv #7 blt rel
mb89630r series 54 n mask options * : pull-up resistors cannot be set for p50 to p53. no. part number mb89635r mb89636r mb89637r mb89p637 mb89w637 mb89pv630 mb89t635r mb89t637r specifying procedure specify when ordering masking set with eprom programmer setting not possible 1 pull-up resistors p00 to p07, p10 to p17, p30 to p37, p40 to p43, p50 to p53, p72 to p74 selectable by pin can be set per pin* fixed to without pull-up resistor 2 power-on reset selection with power-on reset without power-on reset selectable setting possible fixed to with power-on reset 3 selection of the main clock oscillation stabilization time (at 10 mhz) approx. 2 18 /f ch (approx. 26.2 ms) approx. 2 17 /f ch (approx. 13.1 ms) approx. 2 14 /f ch (approx. 1.6 ms) approx. 2 4 /f ch (approx. 0 ms) f ch : main clock frequency selectable setting possible fixed to 2 18 /f ch (approx. 26.2 ms) 4 reset pin output reset output provided no reset output selectable setting possible fixed to with reset output 5 single/dual-clock system option single clock dual clock selectable setting possible mb89pv630-101 single-clock system mb89t635r-101 single-clock system mb89t637r-101 single-clock system mb89pv630-102 dual-clock systems mb89t635r-102 dual-clock systems mb89t637r-102 dual-clock systems
mb89630r series 55 n ordering information part number package remarks mb89635rp-sh mb89t635rp-sh mb89636rp-sh mb89637rp-sh mb89p637p-sh mb89t637rp-sh 64-pin plastic sh-dip (dip-64p-m01) mb89635rpf mb89t635rpf mb89636rpf mb89637rpf mb89p637pf mb89t637rpf 64-pin plastic qfp (fpt-64p-m06) mb89635rpfm mb89636rpfm mb89637rpfm mb89t635pfm 64-pin plastic qfp (fpt-64p-m09) mb89w637c-sh 64-pin ceramic sh-dip (dip-64c-a06) mb89pv630cf 64-pin ceramic mqfp (mqp-64c-p01) MB89PV630C-SH 64-pin ceramic mdip (mdp-64c-p02)
mb89630r series 56 n package dimensions "a" lead no. 64 52 32 0.25(.010) 0.30(.012) 51 33 1 19 20 index typ (.016.004) 0.400.10 1.00(.0394) 0.150.05(.006.002) 18.00(.709)ref 22.300.40(.878.016) (stand off) 0.05(.002)min 3.35(.132)max (.551.008) 14.000.20 (.642.016) 16.300.40 ref 12.00(.472) (.736.016) 18.700.40 20.000.20(.787.008) 24.700.40(.972.016) (.047.008) details of "b" part 1.200.20 0 10 details of "a" part 0.18(.007)max 0.63(.025)max 0.10(.004) "b" m 0.20(.008) 1994 fujitsu limited f64013s-3c-2 c (mounting height) +0.50 C0 C0 +.020 C.022 +.008 C0.55 +0.22 55.118(2.170)ref index-2 15max typ 19.05(.750) (.010.002) 0.250.05 max 1.778(.070) (.070.007) 1.7780.18 1.00 .039 (.018.004) 0.450.10 0.51(.020)min 3.00(.118)min 5.65(.222)max index-1 (.669.010) 17.000.25 2.283 58.00 1994 fujitsu limited d64001s-3c-4 c 64-pin plastic qfp (fpt-64p-m06) dimensions in mm (inches) 64-pin plastic sh-dip (dip-64p-m01) dimensions in mm (inches)
mb89630r series 57 +0.13 C0.08 C.003 +.005 0~9 5.84(.230)max 8.89(.350) dia typ (.134.014) 3.400.36 55.118(2.170)ref (.738.010) 18.750.25 (2.240.022) 56.900.56 (.750.010) 19.050.25 (.010.004) 0.250.05 1.270.25 (.050.010) 1.45(.057) max 1.7780.180 (.070.007) 0.900.10 (.0355.0040) 0.46 .018 index area r1.27(.050) ref 1994 fujitsu limited d64006sc-1-2 c +0.20 C0.10 +.008 C.004 +0.05 C0.02 +.002 C.001 lead no. (stand off) 64 49 48 33 32 17 16 1 nom (.512) ref (.384) 13.00 9.75 (.012.004) 0.300.10 0.65(.0256)typ 12.000.10(.472.004)sq 14.000.20(.551.008)sq (.020.008) (.004.004) 0.100.10 0.500.20 0 10 details of "a" part "a" 1.50 .059 0.127 .005 1 pin index 0.10(.004) m 0.13(.005) 1994 fujitsu limited f64018s-1c-2 c (mounting height) 64-pin plastic qfp dimensions in mm (inches) (fpt-64p-m09) 64-pin ceramic sh-dip (dip-64c-a06) dimensions in mm (inches)
mb89630r series 58 +0.13 C0.08 +.005 C.003 index area 0~9 (.750.012) 19.050.30 0.46 .018 (2.240.025) (.010.002) 0.250.05 (.050.010) 1.270.25 (.135.015) 3.430.38 55.12(2.170)ref (.035.005) 0.900.13 (.070.010) 1.7780.25 10.16(.400)max 33.02(1.300)ref (.100.010) 2.540.25 (.738.012) 18.750.30 typ 15.24(.600) 56.900.64 1994 fujitsu limited m64002sc-1-4 c dimensions in mm (inches) +0.40 C0.20 +.016 C.008 +0.40 C0.20 +.016 C.008 1.20 .047 12.00(.472)typ (.039.010) 1.000.25 typ 18.00(.709) (.039.010) 1.000.25 (.016.004) 0.400.10 1.20 .047 (.016.004) 0.400.10 max 10.82(.426) (.006.002) 0.150.05 0.50(.020)typ 11.68(.460)typ 9.48(.373)typ 7.62(.300)typ 0.30(.012)typ (.050.005) 1.270.13 (.713.008) 18.120.20 typ 14.22(.560) typ 12.02(.473) typ 10.16(.400) typ 24.70(.972) (.878.013) 22.300.33 (.050.005) 1.270.13 typ 0.30(.012) index area 18.70(.736)typ (.642.013) 16.300.33 (.613.008) 15.580.20 1994 fujitsu limited m64004sc-1-3 c dimensions in mm (inches) 64-pin ceramic mqfp (m q p-64c-p01) 64-pin ceramic mdip (m d p-64c-p02)
mb89630r series 59 fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka, nakahara-ku, kawasaki-shi, kanagawa 211-8588, japan tel: +81-44-754-3763 fax: +81-44-754-3329 http://www.fujitsu.co.jp/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, usa tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte ltd #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ f9609 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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